	// verilator_coverage annotation
	module reg_id_ex(
 020001	    input  wire clk,
%000001	    input  wire rst,
 026385	    input  wire[31:0] id_pc,
 112344	    input  wire[31:0] id_regs_data1,
 131974	    input  wire[31:0] id_regs_data2,
 000367	    input  wire[31:0] id_imm,
 000040	    input  wire[2:0]  id_func3_code, 
 006574	    input  wire       id_func7_code,
 019783	    input  wire[4:0]  id_rd,
 006584	    input  wire       id_br,
 000012	    input  wire       id_mem_read,
 000013	    input  wire       id_mem2reg,
 013198	    input  wire[2:0]  id_alu_op,
%000002	    input  wire       id_mem_write,
 000036	    input  wire[1:0]  id_alu_src1,
 000032	    input  wire[1:0]  id_alu_src2,
%000009	    input  wire       id_br_addr_mode,
 000022	    input  wire       id_regs_write,
	
 006569	    input  wire       id_ex_flush,
	
	    //forwarding
 026347	    input wire[4:0] id_rs1,
 013233	    input wire[4:0] id_rs2,
 000078	    output reg[4:0] ex_rs1,
 000096	    output reg[4:0] ex_rs2,
	
 019817	    output reg[31:0]  ex_pc,
 000707	    output reg[31:0]  ex_regs_data1,
 000629	    output reg[31:0]  ex_regs_data2,
 000392	    output reg[31:0]  ex_imm,
 000041	    output reg[2:0]   ex_func3_code, 
%000007	    output reg        ex_func7_code,
 000083	    output reg[4:0]   ex_rd,
 006584	    output reg        ex_br,
 000013	    output reg        ex_mem_read,
 000013	    output reg        ex_mem2reg,
 019767	    output reg[2:0]   ex_alu_op,
%000002	    output reg        ex_mem_write,
 000036	    output reg[1:0]   ex_alu_src1,
 000034	    output reg[1:0]   ex_alu_src2,
 006579	    output reg        ex_br_addr_mode,
 000024	    output reg        ex_regs_write,
	
 000276	    input wire [31:0] id_m_data,
 000291	    output reg [31:0] ex_m_data,
%000003	    input wire id_m_write,
%000002	    output reg ex_m_write,
 006604	    input wire [1:0] id_m_w_index,
 000038	    output reg [1:0] ex_m_w_index,
 006611	    input wire [1:0] id_m_r_index,
 000044	    output reg [1:0] ex_m_r_index,
 026364	    input wire [6:0] id_inst_opcode,
 026368	    output reg [6:0] ex_inst_opcode,
%000242	    input wire [31:0] id_r_matrix_mopa [3:0],
 506041	    output reg [31:0] ex_r_matrix_mopa [3:0],
%000003	    input wire id_matrix_mopa_en,
%000002	    output reg ex_matrix_mopa_en
	);
	always @(posedge clk) begin
 003384	    if (!rst || id_ex_flush)begin
	        ex_pc           <= 0;
	        ex_regs_data1   <= 0;
	        ex_regs_data2   <= 0;
	        ex_imm          <= 0;
	        ex_func3_code   <= 0;
	        ex_func7_code   <= 0;
	        ex_rd           <= 0;
	        ex_br           <= 0;
	        ex_mem_read     <= 0;
	        ex_mem2reg      <= 0;
	        ex_alu_op       <= 0;
	        ex_mem_write    <= 0;
	        ex_alu_src1     <= 0;
	        ex_alu_src2     <= 0;
	        ex_br_addr_mode <= 0;
	        ex_regs_write   <= 0;
	
	        ex_rs1          <= 0;
	        ex_rs2          <= 0;
	        
	        ex_m_data       <= 0;
	        ex_m_write      <= 0;
	        ex_m_w_index    <= 0;
	        ex_m_r_index    <= 0;
	        ex_inst_opcode  <= 0;
	        ex_r_matrix_mopa[0] <= 0;
	        ex_r_matrix_mopa[1] <= 0;
	        ex_r_matrix_mopa[2] <= 0;
	        ex_r_matrix_mopa[3] <= 0;
	        ex_matrix_mopa_en <= 0;
	    end 
 006616	    else begin
	        ex_pc           <= id_pc;
	        ex_regs_data1   <= id_regs_data1;
	        ex_regs_data2   <= id_regs_data2;
	        ex_imm          <= id_imm;
	        ex_func3_code   <= id_func3_code;
	        ex_func7_code   <= id_func7_code;
	        ex_rd           <= id_rd;
	        ex_br           <= id_br;
	        ex_mem_read     <= id_mem_read;
	        ex_mem2reg      <= id_mem2reg;
	        ex_alu_op       <= id_alu_op;
	        ex_mem_write    <= id_mem_write;
	        ex_alu_src1     <= id_alu_src1;
	        ex_alu_src2     <= id_alu_src2;
	        ex_br_addr_mode <= id_br_addr_mode;
	        ex_regs_write   <= id_regs_write;
	
	        ex_rs1          <= id_rs1;
	        ex_rs2          <= id_rs2;
	        ex_m_data       <= id_m_data;
	        ex_m_write      <= id_m_write;
	        ex_m_w_index    <= id_m_w_index;
	        ex_m_r_index    <= id_m_r_index;
	        ex_inst_opcode  <= id_inst_opcode;
	        ex_r_matrix_mopa[0] <= id_r_matrix_mopa[0];
	        ex_r_matrix_mopa[1] <= id_r_matrix_mopa[1];
	        ex_r_matrix_mopa[2] <= id_r_matrix_mopa[2];
	        ex_r_matrix_mopa[3] <= id_r_matrix_mopa[3];
	        ex_matrix_mopa_en <= id_matrix_mopa_en;
	    end
	    $display("ex_regs_data1: %h",ex_regs_data1 );
	    $display("ex_regs_data2: %h",ex_regs_data2 );
	    $display("ex_imm: %h",ex_imm );
	    $display("ex_alu_op: %h",ex_alu_op );
	end
	endmodule
	
